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DFT Implementation

Job Description

Our Client is an international group offering innovation and high-tech engineering consulting services for more than 30 years to key players in the Aerospace, Automotive, Energy, Railway, Finance, Healthcare and Telecoms sectors. Our Client operates in over twenty countries throughout Europe, Asia and the Americas. Every day, we bring our clients' most complex projects to life and we boost their performance through our expertise in technologies and innovation processes. Our Client has contributed to some of the major technological advances in recent decades covering areas of: speed, precision, security, communication, practicality, interoperability, artificial intelligence, etc.

Job Title: DFT Implementation
Experience Range:
4 to 15 Years
Job location: Bangalore

Experienced DFT engineer with good analyzing capabilities with the below skills  : Scan insertion & ATPG

- Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive).  

- Familiarity with WGL/TDL file formats.

- Good skills in Scan compression techniques and Logic BIST.

- Exposure to Memory BIST insertion tools (Preferably LogicVision MBIST).

- Good experience in Boundary Scan, JTAG concepts, Core testing using P1500.

- Should have basic understanding of Tester requirements.

- Should be good at doing synthesis  and timing (RC and PT/Tempus).

- Knowledge of formal verification using LEC.

- Exposure to SoC level DFT will be a plus.

 -Experience on low power DFT is an added advantage.



Resumes must be in word format mentioning your Present CTC,  Expected  CTC & Joining Time

APPLY to resume@careeredgetech.com