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Physical Design Lead

Job Description

Our Client is an international group offering innovation and high-tech engineering consulting services for more than 30 years to key players in the Aerospace, Automotive, Energy, Railway, Finance, Healthcare and Telecoms sectors. Our Client operates in over twenty countries throughout Europe, Asia and the Americas. Every day, we bring our clients' most complex projects to life and we boost their performance through our expertise in technologies and innovation processes. Our Client has contributed to some of the major technological advances in recent decades covering areas of: speed, precision, security, communication, practicality, interoperability, artificial intelligence, etc.

Job Title: Physical Design Lead
Experience Range: 6 to 15 Years
Job location: Bangalore

-   Strong back ground of ASIC physical design: Floor planning, P&R, extraction, IR Drop Analysis, timing and signal Integrity closure

-   Extensive experience and detailed knowledge in Cadence or Synopsys or Magma Physical Design Tools

-   Expertise in scripting languages such as PERL, TCL strong physical verification skill set. Static timing analysis in Primetime or Primetime-SI

-   Desired skills- Expertise in full chip physical design

-   Provide technical guidance, mentoring to Physical Design Engineers Interface with front-end ASIC teams to resolve issues

-   Low Power Design - Voltage islands, power gating, substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces

-   Should be able to do top-level floor planning, PG planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks(DRC), and Logical vs. Schematic (LVS) checks, antenna checks

-   Should have worked on 65nm or lower node designs with advance low power techniques such as voltage islands, power gating and substrate-bias

- Experience in backend flow including physical design, timing analysis to final tape out in 28nm and below. Hands on experience in standard backend tool flows is a must.

-       Excellent communication skills


Resumes must be in word format mentioning your Present CTC,  Expected  CTC & Joining Time

APPLY to resume@careeredgetech.com