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STA Engineers


Our Client is an international group offering innovation and high-tech engineering consulting services for more than 30 years to key players in the Aerospace, Automotive, Energy, Railway, Finance, Healthcare and Telecoms sectors. Our Client operates in over twenty countries throughout Europe, Asia and the Americas. Every day, we bring our clients' most complex projects to life and we boost their performance through our expertise in technologies and innovation processes. Our Client has contributed to some of the major technological advances in recent decades covering areas of: speed, precision, security, communication, practicality, interoperability, artificial intelligence, etc.

Job Description

Job Title: STA Engineers
Experience Range:
4 to 10 Years
Job location: Bangalore


  • You will be part of a Physical Design / Timing Closure team for projects with GHz freq range and cutting edge technologies.
  • You will develop timing constraints for full chip or block level and be responsible for STA signoff for a complex multi-clock, multi-voltage SoCs.
  • You will be responsible for Synthesis, Timing Analysis (STA), CTS at Full Chip or block level for technology nodes of 28nm/14nm.

Desired Skills and Experience:

·         B. Tech. / M. Tech. with 4-10 years of experience in Synthesis, STA

·         Expertise in synthesis of complex SoCs at block/top level and writing timing constraints for complex designs with multiple clocks and multiple voltage domains

·         Expertise on post layout timing closure for multiple tape outs, including timing ECOs and STA signoff

·         Expertise in I/O constraints developments for Industry standard protocols (e.g. DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display etc...)

·         Hands-on experience of working on technology nodes like 28nm, 20nm, 14nm, 10nm

·         Good knowledge of EDA tools from RC, DC, PT, PTSI

·         Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints 

·         Good knowledge of VLSI process and device characteristics

·         Good understanding of deep submicron parasitic effects, crosstalk effects etc.

·         TCL, perl scripting


Resumes must be in word format mentioning your Present CTC,  Expected  CTC & Joining Time

APPLY to resume@careeredgetech.com